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<div class="header">
  <div class="headertitle"><div class="title">DAC_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Digital to Analog Converter.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
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Public Attributes</h2></td></tr>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Digital to Analog Converter. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a9394949a84c836614c6010809e8fe52f">&#9670;&#160;</a></span>CCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DAC_TypeDef::CCR</td>
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<p>DAC calibration control register, Address offset: 0x38 </p>

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<p>DAC control register, Address offset: 0x00 </p>

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<p>DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C </p>

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<p>DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 </p>

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<p>DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 </p>

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<p>DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 </p>

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<p>DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 </p>

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<p>Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 </p>

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<p>DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 </p>

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<p>DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C </p>

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<p>DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 </p>

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<p>DAC channel1 data output register, Address offset: 0x2C </p>

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<p>DAC channel2 data output register, Address offset: 0x30 </p>

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<p>DAC mode control register, Address offset: 0x3C </p>

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<p>DAC Sample and Hold hold time register, Address offset: 0x48 </p>

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<p>DAC Sample and Hold refresh time register, Address offset: 0x4C </p>

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<p>DAC Sample and Hold sample time register 1, Address offset: 0x40 </p>

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<p>DAC Sample and Hold sample time register 2, Address offset: 0x44 </p>

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<p>DAC status register, Address offset: 0x34 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4ccb66068a1ebee1179574dda20206b6">&#9670;&#160;</a></span>SWTRIGR</h2>

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<p>DAC software trigger register, Address offset: 0x04 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
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